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DLANET.DOC
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1990-05-21
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DLANET - Polynomial and Circuit Analysis Program
Version 1.0, April 1987
Copyright - C - 1987, L. P. Huelsman, All rights
resrved.
The required input-output file format for the turbopascal
version of the DLANET program follows. Note: Use Capital
letters as indicated.
Line# Function Comments
1 Title up to 10 ASCII characters.
2 POL or CIR POL for polynomial analysis.
CIR for network analysis.
3 RAD or HZ RAD for a frequency in Radians per seconds.
HZ for a frequency in Hertz.
4 LIN or LOG LIN for a linear frequency scale.
LOG for a logarithmic frequency scale.
5 FRQ xxx yyy Frequency range where
xxx is the lower frequency.
yyy is the upper frequency.
6 MAG yyy scal Ordinate range for the magnitude plot.
yyy is the upper ordinate value.
the lower ordinate value is yyy-90.
scal is a multiplicative constant.
option: if yyy = 999, the scaling is
automatic.
7 NDB or DB DB for a decibel ordinate scale for MAG.
NDB for a non-dB (linear) scale for MAG.
8 PHS yyy scal Ordinate range for the phase on the plot.
yyy is the upper ordinate value.
the lower ordinate value is yyy-90.
scal is a multiplicative constant.
option: if yyy = 999, the scaling is
automatic.
9 PLT or PRT PLT for a plot on the screen.
PRT for both a plot and a file writing.
IF Polynomial Analysis:
10 m n H0 Numerator degree, Denominator degree,
Multiplicative constant.
11 to (11+m) Coefficients of the numerator.
(11+m+1) to (11+m+n+1) Coefficients of the denominator.
(11+m+n+2) END End command.
IF Circuit Analysis:
10 to whatever...
Rn xx yy zz Resistor number n connected from
node xx to node yy with value zz.
Cn xx yy zz Capacitor number n connected from
node xx to node yy with value zz.
Ln xx yy zz Inductor number n connected from
node xx to node yy with value zz.
Vn xx yy zz VCVS number n with input node xx,
output node yy, and gain zz.
Dn xx yy zz tt DVVS number n with positive input
node xx, neg inp node yy, to
output node zz with gain tt.
On xx yy zz Op Amp number n with positive input
node xx, neg inp node yy, and
output node zz.
Last Line END To mark the end of the file.
Comments: After each command or entry followed
by a blank character, the remainder of the line
can be filled up with any ASCII text which is ignored
when the file is read by DLANET.
The DLANET error messages and suggestions to avoid these mistakes.
Some of these errors are obvious mistakes from the user when
connecting active elements. They may be short circuits, operation in
saturation modes, or nonsenses. Other errors occur because of
constraints in the algorithm for the reduction of the matrix. In that
case, the user has to rearrange the circuit so that the reduction
algorithm is actually working. In the next section are a few hints
to have the constraints satisfied.
User related error messages:
Error # 1 : A node number is negative.
Error # 2 : A node number is too large for an active element.
For the active elements, the node numbers can't be
larger than the largest node number for the
passive circuit.
Error # 3 : Output of the active element either grounded or
connected to the input. Implies a short circuit.
Error # 4 : Two ideal source outputs tied together. Short Ckt.
Error # 5 : Zero gain of a VCVS or DVVS. Nonsense.
Error # 6 : Input of a VCVS grounded. Nonsense.
Error # 7 : Zero differential voltage for a DVVS or Op Amp.
Error # 8 : Input connected to own output on VCVS. Short Ckt.
Error # 9 : Direct feedback on DVVS or Op Amp. Unstable.
Error #10 : Direct relation between the network input and its
output. Nonsense.
Algorithm related error messages:
Error #11 : A specific element can not be reduced. Its nodes
either can't be deleted or have already been
deleted by other elements.
Error #12 : A specific element could be reduced with some extra
added components. See the hints in Appendix C.
Error #13 : The output of an active element can not be
connected to the highest node number. This is a
constraint from the matrix inversion algorithm.
Some very useful hints when the user is not used to the DLANET program:
To avoid an unnecessary waste of user time, here are some
hints and further explanations to help him:
From DOS, before running the DLANET.COM file, it would be a
very good idea to run the GRAPHICS.COM command in case the user
wants later to print on his printer the high resolution plots.
From DLANET, when a memory file is ready to be analysed, it is
better to save it to disk under a dummy name, so that if there is a
fatal error, all the editing procedure does not have to be done
again. A simple disk load is enough.
It is much faster to edit a disk input file in compliance with
the format described in appendix A using an external editor or word
processor, and to use the menudriven editor for small changes only,
rather than using this specialised editor for editing a whole new
file from inside the program.
For the multiplot option, the best and fastest procedure, is to
have all the plots ready, either on a file, or from the menudriven
editor. The procedure is to clear the plot memory, set the option to
store all the coming plots, and run all of them one by one, up to
five of them. A screen dump to the printer can be done at any time.
The node assignment for a passive circuit is straight forward
and rather uncritical. The only requirements are that the input
node is 1, the output node is 2, the ground is node 0. If there are
n nodes, they must be numbered from 1 to n, without anyone left.
With active elements, the user has to know that some nodes will
be deleted in the reduction method. One node disappears for each
active element according to a certain procedure.
For a VCVS, the computer tries first to delete the output node.
If it can't, the next try is the input node. For DVVS, it first
tries the output node, then the positive input node, and then the
negative one. For the Op Amps, it tries first the positive input
node, then the negative one.
A problem occurs if for any element, the computer can not
delete any of its nodes. A node can't be deleted if it's either the
ground, network input or output nodes, or highest node number. Also
if it has already been deleted by another element.
To avoid such problems, the user can simulate by hand the
reduction process, and see whether there are problems, and if any,
either rearrange the network or node numerotation, or add passive
elements in series with the infinite impedance input nodes of the
concerned elements. In that last case, the best way is to add a
resistor which value is matched with the other resistors of the
network.